Generally, software enables flexible design change to offer high versatility, but consumes much processing time in executing a task, inviting increased power consumption. Dedicated hardware, such as an application specific integrated circuit (ASIC), achieves high-speed processing to shorten the processing time required for executing a task and thus can reduce power consumption, but lacks versatility in that design change is difficult.
Reconfigurative hardware, such as a field programmable gate array (FPGA), falls between the above software and dedicated hardware. Reconfigurative hardware has features of high-speed processing and low power consumption, and further offers a software-oriented feature of enabling circuit configuration rewriting.
In recent years, techniques using such reconfigurative hardware have been provided, by which hardware is programmed during the execution of a task to dynamically reconfigure a circuit configuration (see, e.g., Japanese Laid-Open Patent Publication Nos. 2006-215592 and H10-320376). According to these techniques, circuit configuration is dynamically reconfigured to realize many functions using few hardware resources and configure a circuit offering various functions to speed up processing.
However, with the conventional techniques described in the above patent documents, hardware reconfiguration itself consumes much time resulting in a time lag until the execution of a task begins, leading to a problem of a drop in output response.
A problem of the conventional techniques will be described in detail with respect to moving image reproduction as an example. FIG. 13 is an explanatory diagram depicting a problem of the conventional techniques. In FIG. 13, a graph 1310 and a graph 1320 depict a change in quality (e.g., image quality) that results upon reproduction of a moving image. In the graphs 1310 and 1320, the vertical axis represents quality and the horizontal axis represents time.
The graph 1310 depicts a change in the quality of a moving image in a case where sequential reconfiguration of hardware (“HW” in FIG. 13) is necessary. In this case, a blank screen continues from the issue of a moving image reproduction instruction to the completion of hardware reconfiguration, and then a clear moving image “quality q4” is reproduced at a time t3.
In other words, a blank screen is displayed for a while after the issue of the reproduction instruction, which results in a drop in output response. As a result, the user views a blank screen for a while after the issue of the reproduction instruction, thus may experience stress because of the delay in the display of the moving image.
The graph 1320 depicts a change in the quality of a moving image in a case where reproduction is alternatively executed by software (“SW” in FIG. 13) before the completion of hardware reconfiguration. In this case, a low-quality moving image “quality q1” is reproduced from the issue of a moving image reproduction instruction until the completion of hardware reconfiguration, and then a clear moving image “quality q4” is reproduced at the time t3.
In other words, the low-quality moving image is displayed for a while after the issue of the reproduction instruction, which results in a drop in output response. Consequently, the user views the low-quality moving image for a while after the issue of the reproduction instruction and thus may experience stress because the display of the moving image is difficult for the user to see.